A Question About Constraints

You can use the following ... basically you cut the timing paths to tell TimeQuest not to analyze them. The cutting of the reset path assumes you have reset synchronizers in your logic (read about reset synchronization in the Quartus handbook). The JTAG paths appear when you use SignalTap II or use the JTAG-to-Avalon-MM bridge.

#  -----------------------------------------------------------------#  Clock#  -----------------------------------------------------------------# #  50MHz clock
set clk_period 50MHz
#  External 50MHz clock (internal logic clock)
set clk clkin_50MHz
create_clock -period $clk_period -name $clk 
#  Exclusive clock domain/group
set_clock_groups -exclusive -group 
#  Derive the clock uncertainty parameter
derive_clock_uncertainty
#  -----------------------------------------------------------------#  JTAG#  -----------------------------------------------------------------# 
set ports 
if { == 1} {
   #  JTAG must be in use
   # 
   #  Exclusive clock domain
    set_clock_groups -exclusive -group altera_reserved_tck
   #  Altera JTAG signal names
    set tck altera_reserved_tck
    set tms altera_reserved_tms
    set tdi altera_reserved_tdi
    set tdo altera_reserved_tdo
   #  Cut all JTAG timing paths
    set_false_path -from *                -to 
    set_false_path -from  -to *
    set_false_path -from  -to *
}
#  -----------------------------------------------------------------#  Cut timing paths#  -----------------------------------------------------------------# #  The timing for the I/Os in this design is arbitrary, so cut all#  paths to the I/Os, even the ones that are used in the design,#  i.e., reset and the LEDs.# 
#  External asynchronous reset and push-buttons
set_false_path -from }] -to *
#  LED output path
set_false_path -from * -to }]