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Altera_Forum's avatar
Altera_Forum
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11 years ago

A Question About Constraints

I understand the clock constraining. But what about the non-clock signals. For example, I have a small VHDL design (1 file) that has a several clocks, a reset, and some LED output signals. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Thanks to both of you. Very helpful.

Yes, I have a SignalTap. That thing caused cause 50 or more JTAG signals to appear from nowhere!