Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

A problem of FSM

The verilog code below is a FSM I designed . I find this FSM can run correctly and jump between different states at first , but after running several seconds it will fall into a fixed state(state...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

@sanmao

1)There is only one SELF_RESET instance in my project. The 10MHz clock is the main clock in the project and

the 90MHz clock is only used in one module.

2)I will rewrite the SELF_RESET code as you suggested.

@FvM

1) I have check the pll "locked" signal after the FSM problem appears, it is in high level . So ,the 90MHz

clock is stable.

2)/*synthesis syn_encoding = "safe"*/ added behind "state" definition can work in Quartus2? Does it have the same effect as "default" item in case statement?