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Altera_Forum's avatar
Altera_Forum
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16 years ago

A problem of FSM

The verilog code below is a FSM I designed . I find this FSM can run correctly and jump between different states at first , but after running several seconds it will fall into a fixed state(state...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

@FvM

The code for the FSM (with the addition of the "default:" in all case statements) as suggested by jacobjones should work.

Once started up the FSM from the "SELF_RESET" the FSM should operate without the problems mentioned by tigre.

@tigre

Is the behavior (after several seconds) that you describe occuring with the "SELF_RESET" that you posted before?

1) If YES. Why do you generated the "SELF_RESET" from a 10MHz clock unrelated to the 90MHz CLK?

2) If NO. I suppose that you are generating a RESET at several instances from an external signal in the 10MHz clock domain. If this is the case, your design can be influenced by races. (for a solution see my previous post).