A problem of FSM

I don't see a reason for the reported behaviour in the posted code. Because no asynchronous events are processed in the FSM (which is the most likely cause for FSM erratic behaviour), PLL loss of lock should be considered.

Although a reliable design operation can't be expected with an unstable clock, you can prevent FSM lockup in illegal states by specifying safe FSM in general synthesis options or synthesis attributes. To make safe FSM coding effective, both state machines should have default states.

This is the respective Verilog syntax for specifying safe state machine synthesis

reg  state /* synthesis syn_encoding = "safe" */;
reg  state2 /* synthesis syn_encoding = "safe" */;