Honored Contributor
Honored ContributorHi tigre,
1) It is good design practice to always provide an external reset signal to your system. This is definitly required when you are targeting an ASIC design. 2) On an FPGA where the registers are initialized to a known state after configuration, you can of course provide a "Power Up" reset signal as you are doing. 3) Your design is working in two different clock domains, that are unrelated. You have one external clock of 10MHz and a second unrelated clock of 90MHz generated by a PLL from a separte 15MHz signal. When you are resting your circuit operating at 90MHz by a reset signal that is generated from an unrelated 10MHz clock, there is no direct correlation between the arrival of the RESET signal and the 90MHz CLK clock signal. This means that your RESET signal will be "racing" with the CLK signal to arrive first at the specific registers in your design. Depending on the specific wiring configuration obtained during the Fitting of your design, it can occur that some registers get reset and other do not. So the behavior that you describe is to be expected. Operating among clock domains is not trivial and you can always suffer from metastability. You can at least improve the behavior of your FSM by "synchronizing" your RESET signal via a number of registers in a chain. This could for example be done as follows for your design:reg RESET, RESET1;
wire RESET2;
always @(posedge CLK) begin
RESET = RESET1;
RESET1 = RESET2;
end
SELF_RESET u1 (clock, RESET2);
