A problem of FSM

Thank you very much for your suggestions!

Following facts may give you more information about this problem:

1.The compilation report shows the timing is meeted.

2.The "RESET" sigal is generated from following module:

module SELF_RESET(// power on reset

input CLK10,

output reg SELF_RESET

);

reg [3:0] count;

always @(posedge CLK10)

begin

if(count != 10)

begin

count <= count + 1;

SELF_RESET <= 1'b1;

end

else

SELF_RESET <= 1'b0;

[/INDENT]end

[/INDENT]

endmodule

The CLK10 is 10MHz.The CLK in FSM is a 90MHz clock generated from a PLL in the FPGA with the input of 15MHz . Both the 10MHz and 15MHz are inputs of FPGA and these two clocks are in different clock domain.

3. Whatever signal cause the FSM jump into a state which is not exist or unwanted , the FSM should can jump out of this state according to the logic.

For example, when the state is changed to 7, FSM should jump into the default state and then jump into state 1. When the state is changed to 0, it also can come out of state o and jump into state 1. But the fact is once the FSM fall into state 7 or state 0 after running correctly for several seconds, it

will never come out again.

Is my understanding about this FSM correct?