A problem of FSM

According to your code, there is no state 7. That would therefore be impossible. Also there is no state2 == 4. Also impossible. The only way this can be happening is if there is some input to the system not illustrated in the code that affects the state machine. That input may be an upset caused by the fact that you're not meeting timing. Are you meeting timing requirements?

reg  state;
reg  state2;
reg  count;
always @(posedge CLK or posedge RESET) begin
    if(RESET) begin //power on reset
                    state <= 0;
                    state2 <= 0;
                    count <= 0;
    end else begin
        case (state)
        0:
            case (state2)
            0: begin
                    count   <= count + 1;
                if(count == 2) begin
                    state2  <= 1;
                    count   <= 0'
                end
            end
            1: begin
                    count   <= count + 1;
                if(count == 6) begin
                    state2  <= 2;
                    count   <= 0'
                end
            end
            2: begin
                    count   <= count + 1;
                if(count == 6) begin
                    state2  <= 3;
                    count   <= 0'
                end
            end
            3: begin
                    count   <= count + 1;
                if(count) begin
                    state   <= 1;
                    state2  <= 0;
                    count   <= 0;
                end
            end
            endcase
        1:          state <= 2;
        2:          state <= 3;
        3:          state <= 4;
        4:          state <= 5;
        5:          state <= 6;
        6:          state <= 1;
        default:    state <= 0;
        endcase
    end
end