Forum Discussion
PonPon
New Contributor
New Contributor2DFF synchronizer output was determined to be a clock by timing analyzer
Hello everyone, I'm the newbie in FPGA. I want to design a frequency counter, so the design will involved some CDC problem. Therefore, I used FIFO(I use the quartus fifo ip) and 2DFF synchronizer i...
sstrell
Super Contributor
Super ContributorYou have the output of the synchronizer connected to the rdclk and wrclk inputs of 2 FIFOs. Is that intentional? If so, that is considered a clock and needs a create_generated_clock constraint.
PonPonYes, I want the output of the synchronizer to be rdclk and wrclk of 2 FIFOs.
If I want to do this, how to correctly constraint this signal with create_generate_clock command?
