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PonPon's avatar
PonPon
Icon for New Contributor rankNew Contributor
1 year ago

2DFF synchronizer output was determined to be a clock by timing analyzer

Hello everyone, I'm the newbie in FPGA. I want to design a frequency counter, so the design will involved some CDC problem. Therefore, I used FIFO(I use the quartus fifo ip) and 2DFF synchronizer i...
Timing
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
1 year ago

You have the output of the synchronizer connected to the rdclk and wrclk inputs of 2 FIFOs. Is that intentional? If so, that is considered a clock and needs a create_generated_clock constraint.

  • PonPon's avatar
    PonPon
    Icon for New Contributor rankNew Contributor
    1 year ago
    Yes, I want the output of the synchronizer to be rdclk and wrclk of 2 FIFOs.

    If I want to do this, how to correctly constraint this signal with create_generate_clock command?