2DFF synchronizer output was determined to be a clock by timing analyzer

I also gives you my sdc file:

## Generated SDC file "R_fcnt_test.out.sdc"

## Copyright (C) 2018 Intel Corporation. All rights reserved.
## Your use of Intel Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Intel Program License
## Subscription Agreement, the Intel Quartus Prime License Agreement,
## the Intel FPGA IP License Agreement, or other applicable license
## agreement, including, without limitation, that your use is for
## the sole purpose of programming logic devices manufactured by
## Intel and sold by Intel or its authorized distributors. Please
## refer to the applicable agreement for further details.

## VENDOR "Altera"
## PROGRAM "Quartus Prime"
## VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition"

## DATE "Mon Sep 30 20:02:41 2024"

##
## DEVICE "5CSEBA6U23I7"
##

#**************************************************************
# Time Information
#**************************************************************

set_time_format -unit ns -decimal_places 3

#**************************************************************
# Create Clock
#**************************************************************

create_clock -name {clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clk}]
create_clock -name {fin} -period 12500.000 -waveform { 0.000 6250.000 } [get_ports {fin}]
create_clock -name {altera_tck} -period 1000.000 -waveform { 0.000 500.000 } [get_ports {altera_reserved_tck}]
create_clock -name {altera_tdo} -period 10.000 -waveform { 0.000 5.000 } [get_ports {altera_reserved_tdo}]

#**************************************************************
# Create Generated Clock
#**************************************************************

create_generated_clock -name {gate} -source [get_ports {clk}] -divide_by 50000 -master_clock {clk} [get_keepers {gate:G1|gate}]
create_generated_clock -name {fin_div2} -source [get_ports {fin}] -divide_by 2 -master_clock {fin} [get_pins {D1|out_freq|q}]

#**************************************************************
# Set Clock Latency
#**************************************************************

#**************************************************************
# Set Clock Uncertainty
#**************************************************************

set_clock_uncertainty -rise_from [get_clocks {fin}] -rise_to [get_clocks {fin}] -setup 0.170
set_clock_uncertainty -rise_from [get_clocks {fin}] -rise_to [get_clocks {fin}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {fin}] -fall_to [get_clocks {fin}] -setup 0.170
set_clock_uncertainty -rise_from [get_clocks {fin}] -fall_to [get_clocks {fin}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {fin}] -rise_to [get_clocks {fin}] -setup 0.170
set_clock_uncertainty -fall_from [get_clocks {fin}] -rise_to [get_clocks {fin}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {fin}] -fall_to [get_clocks {fin}] -setup 0.170
set_clock_uncertainty -fall_from [get_clocks {fin}] -fall_to [get_clocks {fin}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {clk}] -setup 0.310
set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {clk}] -hold 0.270
set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {clk}] -setup 0.310
set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {clk}] -hold 0.270
set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {gate}] -setup 0.360
set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {gate}] -hold 0.320
set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {gate}] -setup 0.360
set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {gate}] -hold 0.320
set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {clk}] -setup 0.310
set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {clk}] -hold 0.270
set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {clk}] -setup 0.310
set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {clk}] -hold 0.270
set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {gate}] -setup 0.360
set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {gate}] -hold 0.320
set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {gate}] -setup 0.360
set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {gate}] -hold 0.320
set_clock_uncertainty -rise_from [get_clocks {altera_tck}] -rise_to [get_clocks {altera_tck}] -setup 0.310
set_clock_uncertainty -rise_from [get_clocks {altera_tck}] -rise_to [get_clocks {altera_tck}] -hold 0.270
set_clock_uncertainty -rise_from [get_clocks {altera_tck}] -fall_to [get_clocks {altera_tck}] -setup 0.310
set_clock_uncertainty -rise_from [get_clocks {altera_tck}] -fall_to [get_clocks {altera_tck}] -hold 0.270
set_clock_uncertainty -fall_from [get_clocks {altera_tck}] -rise_to [get_clocks {altera_tck}] -setup 0.310
set_clock_uncertainty -fall_from [get_clocks {altera_tck}] -rise_to [get_clocks {altera_tck}] -hold 0.270
set_clock_uncertainty -fall_from [get_clocks {altera_tck}] -fall_to [get_clocks {altera_tck}] -setup 0.310
set_clock_uncertainty -fall_from [get_clocks {altera_tck}] -fall_to [get_clocks {altera_tck}] -hold 0.270
set_clock_uncertainty -rise_from [get_clocks {gate}] -rise_to [get_clocks {clk}] -setup 0.360
set_clock_uncertainty -rise_from [get_clocks {gate}] -rise_to [get_clocks {clk}] -hold 0.320
set_clock_uncertainty -rise_from [get_clocks {gate}] -fall_to [get_clocks {clk}] -setup 0.360
set_clock_uncertainty -rise_from [get_clocks {gate}] -fall_to [get_clocks {clk}] -hold 0.320
set_clock_uncertainty -rise_from [get_clocks {gate}] -rise_to [get_clocks {gate}] -setup 0.410
set_clock_uncertainty -rise_from [get_clocks {gate}] -rise_to [get_clocks {gate}] -hold 0.380
set_clock_uncertainty -rise_from [get_clocks {gate}] -fall_to [get_clocks {gate}] -setup 0.410
set_clock_uncertainty -rise_from [get_clocks {gate}] -fall_to [get_clocks {gate}] -hold 0.380
set_clock_uncertainty -fall_from [get_clocks {gate}] -rise_to [get_clocks {clk}] -setup 0.360
set_clock_uncertainty -fall_from [get_clocks {gate}] -rise_to [get_clocks {clk}] -hold 0.320
set_clock_uncertainty -fall_from [get_clocks {gate}] -fall_to [get_clocks {clk}] -setup 0.360
set_clock_uncertainty -fall_from [get_clocks {gate}] -fall_to [get_clocks {clk}] -hold 0.320
set_clock_uncertainty -fall_from [get_clocks {gate}] -rise_to [get_clocks {gate}] -setup 0.410
set_clock_uncertainty -fall_from [get_clocks {gate}] -rise_to [get_clocks {gate}] -hold 0.380
set_clock_uncertainty -fall_from [get_clocks {gate}] -fall_to [get_clocks {gate}] -setup 0.410
set_clock_uncertainty -fall_from [get_clocks {gate}] -fall_to [get_clocks {gate}] -hold 0.380

#**************************************************************
# Set Input Delay
#**************************************************************

set_input_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {clk}]
set_input_delay -add_delay -clock [get_clocks {fin}] 0.000 [get_ports {fin}]

#**************************************************************
# Set Output Delay
#**************************************************************

set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[0]}]
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[1]}]
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[2]}]
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[3]}]
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[4]}]
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[5]}]
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[6]}]
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[7]}]
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[8]}]
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[9]}]

#**************************************************************
# Set Clock Groups
#**************************************************************

#**************************************************************
# Set False Path
#**************************************************************

set_false_path -from [get_clocks {fin}] -to [get_clocks {clk}]
set_false_path -from [get_clocks {fin}] -to [get_clocks {gate}]
set_false_path -from [get_clocks {fin_div2}] -to [get_clocks {clk}]
set_false_path -from [get_clocks {fin_div2}] -to [get_clocks {gate}]
set_false_path -from [get_ports {rst_n}] -to [all_registers]
set_false_path -from [get_ports {altera_reserved_tck altera_reserved_tdi altera_reserved_tdo altera_reserved_tms}]

#**************************************************************
# Set Multicycle Path
#**************************************************************

#**************************************************************
# Set Maximum Delay
#**************************************************************

#**************************************************************
# Set Minimum Delay
#**************************************************************

#**************************************************************
# Set Input Transition
#**************************************************************