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josh_bird's avatar
josh_bird
Icon for New Contributor rankNew Contributor
6 years ago

2 different clock domain for input/output data in SPI master?

Dear Sir, I had a SPI_master question needs to be confirmed. For my system, one sys_clk is 50MHz used for main clock and that SPI_master sck_o sync with sys_clk to output. Could I apply another...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,


We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


Best regards,

KhaiY