13 bit counter in VHDL not working :(

Hi..

I have made simple 13 bit counter code.But its not working.I could not able to find any solution.

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

architecture behav of FA_calc is

signal counter : std_logic_vector(12 downto 0) := "0000000000000";

signal clkenable : std_logic;

begin

clkdiv : process(clk)

begin

if clk = '1' and clk'event and clkenable = '1' then

counter <= counter + 1;

end if;

end process;

trans : process(counter)

begin

clkenable <= '1';

if counter = "1101001000000" then

----

----

end case;

counter <= "0000000000000";

clkenable <= '0';

end if;

end process trans;

Warning :- There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).

Whats should i do for that ??Error is because of unsign number i defined "use IEEE.std_logic_unsigned.all but still warning :(

Thanks