13 bit counter in VHDL not working :(

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clkdiv : process(clk)

begin

if clk = '1' and clk'event and clkenable = '1' then

counter <= counter + 1;

end if;

end process;

THe above if statement is not formed correctly.

remove the and clkenable = '1' from the initial if statemetn and place it inside the (clk and clkevent) section.

THe altera tool have a language help section forthese type expressions.