12004 error (everything is set up correctly but I keep getting this error)

library ieee;
use ieee.std_logic_1164.all;

entity dflipflop is
port( D,clk: in std_logic;
Q: out std_logic
);
end dflipflop;

architecture struct of dflipflop is

component dLatch is
port( clk,D : in std_logic;
Q : out std_logic
);
end component;

signal Qm : std_logic;

begin

hex_1 : dLatch port map(D=>D, clk=>S, Q=>Q);


end struct;

library ieee;
use ieee.std_logic_1164.all;

entity dLatch is
port( clk,D : in std_logic;
Q : out std_logic
);

end dLatch;

architecture struct of dLatch is

signal S,R,R_g, S_g, Qa, Qb : std_logic;
attribute keep : boolean;
attribute keep of R_g, S_g, Qa, Qb : signal is true;

begin
S <= D;
R <= not(D);
R_g <= R nand clk;
S_g <= S nand clk;
Qa <= S_g nand Qb;
Qb <= R_g nand Qa;


Q <= Qa;

end struct;