12004 error (everything is set up correctly but I keep getting this error)

UPDATED: first entity has wrong declarations

library ieee;
use ieee.std_logic_1164.all;

entity dflipflop is
port( D,clk: in std_logic;
Q: out std_logic
);
end dflipflop;

architecture struct of dflipflop is

component dLatch is
port( clk,D : in std_logic;
Q : out std_logic
);
end component;

signal Qm : std_logic;

begin

master : dLatch port map(D=>D, clk=>not(clk), Q=>Qm);
slave : dLatch port map(D=>Qm, clk=>clk, Q=>Q);


end struct;