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thank you sir :lol:
Will make sure this code does not reach to him.
In my defense, I wrote this code with just 2 days of reading VHDL book (by Douglas Perry).
Will definitely try and get better at practical design.
if possible can you recommend some books with more practical examples/codes just to get familiar with VHDL.
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For running average: pass input through 4196 stages (registers but memory based fifo is more realistic). accumulate continuously and subtract last stage from result of accum.
The accum is just an adder with feedback from its output. djust bitidth to input bitwidth plus accum growth of 2^13
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