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Altera_Forum's avatar
Altera_Forum
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10 years ago

10 second timer

-I'm trying to make a 10 seconde timer for parking lot "gate", and i need to use a variable (s_count) on a diferente fase of the work (i need to use a sensor that says's if there's a car entering in the parkig lot while the "gate" is still open, and if ther's a car then it stops countig and only start's again when the sensor = '0' (no car) ), and i don't know how, and i could use some help.

Thank you in advance

This is my code so far :

cancela = gate

valida = validation of a card thet gives access to the park.

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.numeric_std.all;

use ieee.std_logic_unsigned.all;

entity Fase1 is

Port (valida: in std_logic; Clk: in std_logic; start: in std_logic; cancela: out std_logic; timerOut: out std_logic);

end Fase1;

architecture RTL of Fase1 is

signal s_cancela : std_logic;

signal s_count : integer := 0;

begin

process(Clk)

begin

if(valida = '1') then

s_cancela <= '1';

if(s_cancela = '1') then

if (start='0') then

s_count <= 0;

timerOut <= '1';

else

if (rising_edge(CLK)) then

if (s_count<=500000000) then

s_count <= s_count+1;

else

timerOut <= '0';

end if; end if; end if; end if;

elsif(valida = '0') then

s_cancela <= '0';

timerOut <= '0';

end if;

cancela <= s_cancela;

end process;

end RTL;

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    I recommend you reformat the code into the recommended process template. Currently your code is missing signals from the sensitivity list so that it's behaviour in simulation will not match that of the real hardware. The asynchronous reset template is: 

    
process(clk, rst) --rst must be included in here for async reset
begin
  if reset = '1' then 
    --reset stuff
  elsif rising_edge(clk) then
    --do logic stuff here
  end if;
  --note NOTHING goes here
end process;
--output assignments go outside the process

    Other than that - what problems are you having? have you created a testbench and tried to simulate the design to help you debug it?