I recommend you reformat the code into the recommended process template. Currently your code is missing signals from the sensitivity list so that it's behaviour in simulation will not match that of the real hardware. The asynchronous reset template is:
process(clk, rst) --rst must be included in here for async reset
begin
if reset = '1' then
--reset stuff
elsif rising_edge(clk) then
--do logic stuff here
end if;
--note NOTHING goes here
end process;
--output assignments go outside the process
Other than that - what problems are you having? have you created a testbench and tried to simulate the design to help you debug it?