Honored ContributorIf you use blocks and bundles and a third party verilog simulator as I do. Stay away from 10.0 for schematic entry. Do the entry in an early version and use 10.0 for compile only. I have been reporting schematic entry bugs as SR to Altera all morning.
Honored Contributorcan you share them here too?
Honored ContributorIn previous Quartus versions the resulting verilog code from a create HDL process would take the module name "case sensitive" from the bdf files root name. It now appears the Quartus lower cases the bdf name resulting in incorrect references in associated shematic reference.
he 10.0 megawizard would not read my 9.0 SP2 generated .v files so that I could easily migrate my IP to the latest version. I had to re-enter all IP parameters from scratch. I have schematics with blocks and bundles (conduit) and the mappings are not working. The bundles have the signals and the mappings are correct but the schematics won't analyze. I have submitted example project cases to Altera. I am currently backing up to 9.1 SP2 and abandoning 10.0
