Forum Discussion
Are you planning to run RTL simulation or a post-fit functional simulation using a netlist?
Unfortunately, I am not familiar with UniPHY IP, however looking at the User Guide, the post-fit functional simulation does not seem to work for the UniPHY IP core. (check section 8.2.8. Post-fit Functional Simulation)
It appears that the post-fit netlist for designs containing UniPHY IP is a hybrid—gate-level for the FPGA core and RTL-level for the external memory interface IP.
You can refer to the simulation walkthrough in the User Guide (link above), using an example design that can be generated with the IP core. Once you're familiar with the simulation flow, cross-check it against your own design to identify any discrepancies.
Additionally, do you use other IP in your design? Which specific IP is causing below error?
Could you provide the error log/transcript ?
# ** Error: (vcom-7) Failed to open design unit file "*PATH*/*TO*/*PROJ*/*IP_name*.vho" in read mode.
Regards,
Richard Tan