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Altera_Forum's avatar
Altera_Forum
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11 years ago

.sdc file for simple IO Ports

Hello all

I am developing a pure custom VHDL project that has an external clock that gets PLLed to a faster clock inside the system and from then on the fast clock is used. This clock is not propagated to any outside chips and it is correctly constrained in my sdc file.

The bad thing is that I am getting Timing warnings for the IO ports which are just used for PWM, ADC and some other functions. How do I constrain the output pins?

Thanks

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Hi,

    The IOs are constrained using set_input_delay and set_output_delay. One constrain with the -min flag and one contrain with the -max flag. In that way you model then valid sampling window for input signals. Similarly you constrain the output to make sure that the window is large enough for the receiveing device. Check the setup and hold requirements in the data sheets of the receiving devices. Note that you use a virtual clock that models the clock in the other device as a reference in the constraint.

    More details about set_input/output_delay is found in the SDC cookbook: http://www.altera.com/literature/manual/mnl_timequest_cookbook.pdf

    Cheers