Forum Discussion
2 Replies
- Altera_Forum
Honored Contributor
Hi,
This type of error may be because of compilation order.Can you elaborate on compilation steps or attach the transcript. Refer below link if may help https://www.altera.com/support/support-resources/knowledge-base/solutions/rd12162013_881.html Let me know if this has helped resolve the issue you are facing or if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation) - Altera_Forum
Honored Contributor
Thank you for helping. This is what I do -
1. Create a qsys system with the platform designer in Q17.1 or 16.1 targeting an Arria10GX device. 2. Create testbench for the system from the Tools menu in the qsys generator. 3. Go to the <component>_tb/sim/mentor in questasim version 10.7a 4. Run msim_setup.tcl. Which creates aliases dev_com, com and elab_debug. 5. I run dev_com, then com and then elab_debug. That’s when I get the error. It doesn’t seem to matter what I put in the qsys. For my test case I have a clock, reset and altera’s quad spi flash programmer ip. To me it seems like there is something wrong in the verilog version of the encrypted twentynm files. While the problem occurs during elab of twentynm_atoms_encrypt.v the encrypted hip file reports incorrect carriage return warning. It may or may not be related. Please help. Cannot go far in creating simulation env if intel provided ip blocks do not work. Thank you. Best regards