WISHBONE AVALON BRIDGE - migration problem ?

Hello,

in former times I used Quartus v9.1 and NIOSII v.9.1 with an Cyclone II FPGA. Actual I use Quartus v10.1 and NIOSII v.10.1 with an Cyclone IV FPGA.

Since I changed both (devleopment software and FPGA), the WISHBONE-AVALON BRIDGE does not work.

In the follwing code, there is VHDL File for mapping the BUS Signals and the TCL file for creating the component in SOPC Builder.

The problem I have is, that NIOS write no valid adresses. In the memory table there are false data.

I did not change all code which deals with the WISHBONE AVALON BRIDGE.

Has anybody an idea what the reason for it can be?

# #################################### ###################################

VHDL - BRIDGE WISHBONE-AVALON# #################################### ###################################

....

WB_ADR <= AV_ADR;

WB_CYC_IN <= AV_CS;

WB_STB_IN <= not AV_WE_N or not AV_RD_N;

WB_WE_IN <= not AV_WE_N and AV_RD_N;

AV_WAITREQ <= not WB_ACK_O;

WB_DAT_O <= AV_DAT_IN;

process(AV_BYTE_EN)

begin

AV_DAT_O <= WB_DAT_IN;

end process;

....

# #################################### ###################################

TCL FILE - Component in SOPC Builder# #################################### ###################################

# +-----------------------------------# | connection point avalon_slave_0# |

add_interface avalon_slave_0 avalon end

set_interface_property avalon_slave_0 addressAlignment DYNAMIC

set_interface_property avalon_slave_0 addressUnits WORDS

set_interface_property avalon_slave_0 associatedClock clock_sink

set_interface_property avalon_slave_0 associatedReset clock_sink_reset

set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false

set_interface_property avalon_slave_0 explicitAddressSpan 0

set_interface_property avalon_slave_0 holdTime 0

set_interface_property avalon_slave_0 isMemoryDevice false

set_interface_property avalon_slave_0 isNonVolatileStorage false

set_interface_property avalon_slave_0 linewrapBursts false

set_interface_property avalon_slave_0 maximumPendingReadTransactions 0

set_interface_property avalon_slave_0 printableDevice false

set_interface_property avalon_slave_0 readLatency 0

set_interface_property avalon_slave_0 readWaitTime 1

set_interface_property avalon_slave_0 setupTime 0

set_interface_property avalon_slave_0 timingUnits Cycles

set_interface_property avalon_slave_0 writeWaitTime 0

set_interface_property avalon_slave_0 ENABLED true

add_interface_port avalon_slave_0 AV_WE_N write_n Input 1

add_interface_port avalon_slave_0 AV_RD_N read_n Input 1

add_interface_port avalon_slave_0 AV_WAITREQ waitrequest Output 1

add_interface_port avalon_slave_0 AV_BYTE_EN byteenable Input 4

add_interface_port avalon_slave_0 AV_ADR address Input 16

add_interface_port avalon_slave_0 AV_DAT_IN writedata Input 32

add_interface_port avalon_slave_0 AV_DAT_O readdata Output 32

add_interface_port avalon_slave_0 AV_CS chipselect Input 1# |# +-----------------------------------

# +-----------------------------------# | connection point clock_sink# |

add_interface clock_sink clock end

set_interface_property clock_sink clockRate 0

set_interface_property clock_sink ENABLED true

add_interface_port clock_sink CLK clk Input 1# |# +-----------------------------------

# +-----------------------------------# | connection point conduit_end# |

add_interface conduit_end conduit end

set_interface_property conduit_end ENABLED true

add_interface_port conduit_end WB_WE_IN export Output 1

add_interface_port conduit_end WB_STB_IN export Output 1

add_interface_port conduit_end WB_CYC_IN export Output 1

add_interface_port conduit_end WB_DAT_IN export Input 32

add_interface_port conduit_end WB_DAT_O export Output 32

add_interface_port conduit_end WB_ACK_O export Input 1

add_interface_port conduit_end WB_ADR export Output 16# |# +-----------------------------------

THANK YOU