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Altera_Forum
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13 years ago

WISHBONE AVALON BRIDGE - migration problem ?

Hello, in former times I used Quartus v9.1 and NIOSII v.9.1 with an Cyclone II FPGA. Actual I use Quartus v10.1 and NIOSII v.10.1 with an Cyclone IV FPGA. Since I changed both (devleopment...
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Altera_Forum
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13 years ago

By handshake signals do you mean read, write, byte enable, etc...? If you are not seeing those transition I would guess it's one of two things:

1) the wiring in the bridge isn't connected and transactions are being lost (doubtful if this worked before)

2) accesses to the bridge are not reaching the slave port and as a result nothing comes out the other side.

If you haven't already done so I would simulate the system so that you can get the big picture of what is going on. Alteratively you could signaltap both sides of the bridge and the master accessing the bridge. You don't need to capture all the signals, probably address, read, and write would be a good set of signals to look at to see if transactions are being lost. If you see something suspect then you can add data to get a better idea what's going on.