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Altera_Forum
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14 years ago

Will Nios II work with 16-bit SRAM?

I have been trying to get an external SRAM chip to work with Nios II for over two weeks with no success. I have tested the SRAM outside of SOPC Builder with a simple VHDL routine that writes to each address then reads back the SRAM data. I used SignalTap to verify that all address and data lines are working.

I also instantiated the SRAM as a custom memory component in SOPC Builder - first with only a JTAG Master and JTAG UART, and then with a simple Nios II system. In both case I can access the SRAM component with System Console and it seems to work fine. However, in the Nios II system, I have to stop the processor to run System Console. Is this normal?

My BIG problem is that I cannot get Nios II to work with the external SRAM component. Specifically, downloading the ELF file fails. I am now wondering if it is because the SRAM has a 16-bit data bus. Do I need to design an HDL component to adapt the 32-bit Nios II data bus to the SRAM 16-bit data bus, or does SOPC Builder/Avalon/Nios II do that for me?

Daixiwen, thepancake, I have read a lot of your posts. From what I've seen you guys must know how to instantiate a simple 16-bit external SRAM component. Can you or someone else please help me?

Many thanks in advance,

fheineman

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  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    Hello,

    What about your system frequency vs the SRAM speed grade ?

    Regards,

    Franck.

    --- Quote End ---

    sys_clk 50MHz,

    SRAM speed grade 10ns.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Good point on the SRAM speed grade. The one I am using is 45ns. This does not seem to be an issue as I have configured the timing - first in a custom component in SOPC Builder, and more recently in the Qsys Generic Tri-State Controller to slow down the interface to the external SRAM. This, by the way, is a very nice feature in Qsys. It takes a lot of the hassle out of interfacing to slow peripheral components.

    Anyway, I finally discovered that the problem I was having in Eclipse of not being able to download an elf file was due to something else and not the SRAM.

    A note to those trying to interface external SRAM, Qsys uses the address lines as though it were addressing bytes, not words. If your external SRAM is 16-bit, the LSB of the Qsys address is held low. The SRAM chip I'm using expects word addressing, so I did not connect the LSB (bit [0]) of the Qsys SRAM address.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    hi

    I want use avalon to external bridge in the sopc builder, but i am unable to see the avalon to external bridge.. can anyone clarify what is the problem..?
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I don't think such a component exists. What are you looking for? Maybe the tristate bridge?

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hi.

    I had the same problem, when I used a SDRAM controller.

    I made a research, I discovered that the problem was the SDRAM chip timing. The SDRAM delays 3ns to response.

    So I configured a PLL with 2 clock outputs, one clock (c0) normal with 50MHz for output without delay and an another clock (c1) with 50MHz for output and 3ns delay.

    I connected the c1 to the NIOS II clock and the c0 to SDRAM clock.

    I'm using a DE0-Nano Board from terasic

    "Sorry about my english, I've been learning just over on year."