Forum Discussion
Altera_Forum
Honored Contributor
13 years agoHi.
I had the same problem, when I used a SDRAM controller. I made a research, I discovered that the problem was the SDRAM chip timing. The SDRAM delays 3ns to response. So I configured a PLL with 2 clock outputs, one clock (c0) normal with 50MHz for output without delay and an another clock (c1) with 50MHz for output and 3ns delay. I connected the c1 to the NIOS II clock and the c0 to SDRAM clock. I'm using a DE0-Nano Board from terasic "Sorry about my english, I've been learning just over on year."