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Altera_Forum's avatar
Altera_Forum
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21 years ago

what's effect of EPM config controller?

hello ,

i know that the EPM is very useful when power up,it can put the .sof that stored in the flash into FPGA,

but, when i config the EPM with an incompatible config_controller.pof, and only "RUN" on the IDE the program, it show error :

There are no Nios II CPUs with debug modules available which match the values

specified. Please check that your PLD is correctly configured, downloading a

new SOF file if necessary.

i want to know the EPM why affect the "RUN" (not Flash programmer)program

thank u!

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    Hello ffone13,

    Is it correct that you indicate EPM with the configuration CPLD which is installed on the development kits from Altera? Normally the flash holds the configuration data of the FPGA (hex-file) and the CPLD is configuring the FPGA during power-up with the data in the flash. If you program the CPLD with an invalid configuring routine the FPGA will not work until you configure it with the Programmer from Quartus II. So when you power up your board and the FPGA will not be configured out of the flash the Nios IDE can’t detect a working Nios system because it is not there. After configuring the FPGA with the Programmer of Quartus II the Nios IDE should detect the Nios system well.

    I hope this helps,

    niosIIuser

    BTW: Please complete your topic at http://www.niosforum.com/forum/index.php?a...ct=st&f=2&t=667 (http://www.niosforum.com/forum/index.php?act=st&f=2&t=667)
  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    hello niosIIuser,

    thank your reply. your meaning "After configuring the FPGA with the Programmer of Quartus II the Nios IDE should detect the Nios system well." Yes, i surely have done it.

    my meaning is that: when before solder the EPM CPLD ,the SRAM and other device is running ok,but after that all device includeing ram on the FPGA are nonavailable. Dose the EPM associate with other device?

    that problem i mention ago is hardware problem. it's hard to say clear.sorry.
  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    Another potential gotcha:

    The config controller configures the FPGA. It does this by actively wiggling signals to the dev board flash such that data is presented to the FPGA for configuration. If your new config controller design doesn't tri-state its IOs that go off to the tri-state bus... bad things (contention, bad data, frying IO buffers) can/will happen.
  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    thank Jesse,

    when i download *.sof with the Programmer of Quartus II ,I found the LED that connected to CONFIG_DONE pin has been illuminated temporarily (normally,illuminated permanently) .

    So, i want to know the in this case if CPLD has not give the authority to the NIOS just now downloaded.