Forum Discussion
Altera_Forum
Honored Contributor
21 years agoHello ffone13,
Is it correct that you indicate EPM with the configuration CPLD which is installed on the development kits from Altera? Normally the flash holds the configuration data of the FPGA (hex-file) and the CPLD is configuring the FPGA during power-up with the data in the flash. If you program the CPLD with an invalid configuring routine the FPGA will not work until you configure it with the Programmer from Quartus II. So when you power up your board and the FPGA will not be configured out of the flash the Nios IDE can’t detect a working Nios system because it is not there. After configuring the FPGA with the Programmer of Quartus II the Nios IDE should detect the Nios system well. I hope this helps, niosIIuser BTW: Please complete your topic at http://www.niosforum.com/forum/index.php?a...ct=st&f=2&t=667 (http://www.niosforum.com/forum/index.php?act=st&f=2&t=667)