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originally posted by david_cai@Aug 1 2006, 09:37 AM
i guess that you must have one timer which will reset system when timeout occurs. when debugging, for example, application code stop by breakpoint, but the timer still works, when timeout, it will reset system ,then ide will report that watchdog timeout...
fyi.
david
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I completely agree with you, David. However this is essencially my problem. I can't find what timer or component could be causing the problem. As far as I know, a timer configured with 'Writeable Period' and 'Start/Stop control bits' registers (Full-featured preset configuration) resets the counter when period timeouts but never the system.
Another info that could help you and others nios users to help me: Always I try to use ssram to store data and instructions (.rodata, .rwdata, etc..), I have problems with debug too, and the watchdog error is reported just in the terminals of the cpus that are coneccted to ssram. How could ssram be affecting watchdog?
Thanks again!