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Altera_Forum's avatar
Altera_Forum
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15 years ago

VHDL modulo operator causes "Nios Verify failed" - But why?

Hello,

I have curious problem...

In my design I have a TSE which is feed by my own VHDL logic. Further there is a Nios which configures TSE. That's it.

Everything works fine. BUT, when adding a modulo operation like

a := b mod c;

Eclipse says "Verify failed between address 0x40000 and 0x4FFFF" during programming. When removing and replacing this modulo operation with simple logic, everything works fine again.

I can't understand this, because my own VHDL logic has now memory mapped interface. So there isn't any relationship between my own VHDL logic and the OnChip-Memory 0x40000 to 0x4FFFF.

Does anybody has any idea???

Thanks for really every hint...

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    the mod operator synthesises to a very complicated circuit, and with what you are doing it is attemting to compute the result in 1 clock cycle. Im guessing that because of this, it cannot generate "a" in time, and so whatever "a" drives is wrong.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Did you configure Timequest correctly with your timing constraints? I agree with Tricky that the complexity of this operator probably synthesize in logic that is too slow, but Timequest should have spotted this.