Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

VHDL modulo operator causes "Nios Verify failed" - But why?

Hello, I have curious problem... In my design I have a TSE which is feed by my own VHDL logic. Further there is a Nios which configures TSE. That's it. Everything works fine. BUT, whe...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

the mod operator synthesises to a very complicated circuit, and with what you are doing it is attemting to compute the result in 1 clock cycle. Im guessing that because of this, it cannot generate "a" in time, and so whatever "a" drives is wrong.