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Altera_Forum
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16 years ago

VHDL modulo operator causes "Nios Verify failed" - But why?

Hello, I have curious problem... In my design I have a TSE which is feed by my own VHDL logic. Further there is a Nios which configures TSE. That's it. Everything works fine. BUT, whe...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Did you configure Timequest correctly with your timing constraints? I agree with Tricky that the complexity of this operator probably synthesize in logic that is too slow, but Timequest should have spotted this.