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Altera_Forum
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20 years ago

Verilog DMA Controller

Hey there,

I'm trying to create a state machine that will properly control a DMA which reads from SDRAM and writes into on-chip memory.

The transfer width is 32-bit word only, and the total on-chip memory is 1600 bytes (or 0x190 addresses, with two 800 byte halves and 0xC8 being the start of the second half).

I essentially want it to read sequentially from SDRAM address 0x0, placing 800 bytes at a time into each half of the cache.

Currently, my state machine sends out these commands:

write 0x0 into address 1 of the DMA (SDRAM read address)

then later and repetitively,

write 0x320 (decimal 800 - in bytes) into address 3 for the length of the transaction

write 0x0 OR 0xC8 into address 2 of the DMA (on-chip write address, depending on which page I want to overwrite)

write 0x8C into the control register at address 6 (LEEN, GO, and WORD high)

It uses waitrequest and does not violate that timing. However, looking at the waveform in ModelSim, the control register shows that it never changes from 0x84 (LEEN and WORD); in other words, it never performs any transaction.

Any suggestions?

Thanks,

--Dan Healy

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    --- Quote Start ---

    originally posted by hippo@Jan 17 2006, 04:43 PM

    are you using the ref design of avalon microsequencer ?

    http://www.altera.com/end-markets/refdesig...-avl-micro.html (http://www.altera.com/end-markets/refdesigns/sys-sol/indust_mil/ref-avl-micro.html)

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=12254)

    --- quote end ---

    --- Quote End ---

    Nope, I read up on the Avalon bus and implemented those signals within my custom logic, and created an SOPC builder component. The dma_control_master port in my component connects to the control_port_slave port on the DMA.

    That&#39;s a cool link, though...

    Anyway, after looking at the internal DMA signals (i.e. staring at ModelSim until lightbulbs went off), I figured out that it&#39;s actually just not getting the proper address.

    I send it a 32-bit address, 0x00000003, and it reads a 3-bit address 0b000. When I send it address 0x00000006, it reads 0b001. So my guess right now is that it&#39;s somehow getting address [4:2] instead of [2:0] for some reason.. about to give that a try. Doesn&#39;t really make sense, but the problem is definitely in the address...
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    --- Quote Start ---

    originally posted by rhaikh@Jan 17 2006, 06:21 PM

    nope, i read up on the avalon bus and implemented those signals within my custom logic, and created an sopc builder component. the dma_control_master port in my component connects to the control_port_slave port on the dma.

    that&#39;s a cool link, though...

    anyway, after looking at the internal dma signals (i.e. staring at modelsim until lightbulbs went off), i figured out that it&#39;s actually just not getting the proper address.

    i send it a 32-bit address, 0x00000003, and it reads a 3-bit address 0b000. when i send it address 0x00000006, it reads 0b001. so my guess right now is that it&#39;s somehow getting address [4:2] instead of [2:0] for some reason.. about to give that a try. doesn&#39;t really make sense, but the problem is definitely in the address...

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=12256)

    --- quote end ---

    --- Quote End ---

    Yep, that was totally it. I&#39;m not sure if I&#39;m going to try changing my address signal to 3 bits from 32, or if I should just left shift all of my address values by two..

    To be clear: I was trying to write to address 3, and it was reading address zero. I sent it address b01100 instead of b011, and sure enough, it read b011 - [4:2] instead of [2:0].
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    You got it. There are two address mapping schem on avalon bus. Peripheral use "native" addressing that are 32bit word aligned, so the port offset address are 0, 4, 8 etc. The other is "memory" addressing, for 8 bits, 16 bits, 32 bits etc.