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Altera_Forum
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20 years ago

Verilog DMA Controller

Hey there, I'm trying to create a state machine that will properly control a DMA which reads from SDRAM and writes into on-chip memory. The transfer width is 32-bit word only, and the ...
Altera_Forum's avatar
Altera_Forum
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20 years ago

You got it. There are two address mapping schem on avalon bus. Peripheral use "native" addressing that are 32bit word aligned, so the port offset address are 0, 4, 8 etc. The other is "memory" addressing, for 8 bits, 16 bits, 32 bits etc.