Using EPCS and CFI for booting - failure

I don't know how I missed that... sorry :(

I don't remeber how it actually works, but there is an option in signaltap to record some signals during the FPGA startup. You should include a signaltap probe on the CPU's data and instruction masters to try and find out what the CPU is doing when it starts, and include it in the configuration you flash in the EPCS. There is an option somewhere to enable so that the probe starts recording as soon as the FPGA goes into user mode, and then you can fire the signaltap application to download the buffer. Hopefully it will help you understand if the CPU is trying to start the application or is stuck somewhere.