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Altera_Forum's avatar
Altera_Forum
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10 years ago

Use SDRAM simultaneously with HSP and FPGA

Hi

I am using Altera DE1 Soc board. I use HPS and the master on Altera Avalon bus and SDRAM controller as slave which is connected to the SDRAM. I can read and write to the SDRAM without any problem. Now, I am wondering if I can access the SDRAM from the FPGA at the same time. If yes, can anyone tell me how to that?

Best,

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    This one... that SDRAM looks like in sharing mode, maybe you could do a quick test by simulate the write from fgpa and read back from hps for the same memory address for confirmation :D:D

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    --- Quote Start ---

    This one... that SDRAM looks like in sharing mode, maybe you could do a quick test by simulate the write from fgpa and read back from hps for the same memory address for confirmation :D:D

    --- Quote End ---

    Thanks for the reply. I cannot, in Qsys, either I have to connect the S1 from the SDRAM controller to HPS or I have to export it to the FPGA. So, that is where I am not sure what to do.