USB External Chip

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Has anyone had any experience with interfacing to an external (to the gate array) USB Chip ? I am looking for a simple, cheap, low power chip that interfaces directly to a NIOS or even better to Internal Memory. I know that there are USB controllers available that will do the job (I am currently looking into an Cycpress chip that has a 8051 controller, and it will do the job, however it might be a little "over kill". We don't need as many features as are offered there in!). We have also investigated a USB-to-serial chip which will also do the job, but we would prefer a direct USB connection.

Anyone got any ideas ?

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Your decision needs to be based on the interface speed you need.

The FTDI FT245 and FT2232 series have parallel FIFO modes that can be used to send traffic at 1MB/s (asynchronous FIFO mode) and 25MB/s (synchronous FIFO mode).

The Cypress FX2 is a USB 2.0 device with a pretty flexible general purpose bus interface. Unfortunately, it has an 8051 as a processor. Its not exactly the nicest processor to code and run an RTOS on.

The Cypress FX3 looks pretty nice. There is a new board from Arrow called the BeUSB 3.0 which plugs into the BeMicro-SDK and BeMicro boards.

http://components.arrow.com/manufacturers/cypress-semiconductor/

I purchased one, but have not had time to play with it. Yes, this is also probably overkill, but its another option to consider ...

Cheers,

Dave

Thanks for all your informative answers :).

As an option, can any of these solutions be implemented without a NIOS and interfaced to memory internal to the SOPC builder via VHDL code? I am looking to cut power as much as we can. However I am not certain if such a design will in fact take so much less power?

I assume that if we use a USB controller like the FX2 with the 8051 built in, it will be able to transfer the USB data to my memory internal to the SOPC system with no other internal interfacing required thus reducing the power requirements ?

However there may be additional glue logic needed since there will be another NIOS attached this this internal memory and thus some sort of arbitration will be required. See the thread below

http://www.alteraforum.com/forum/showthread.php?p=155961#post155961 (http://www.alteraforum.com/forum/showthread.php?p=155961#post155961)

So I am not sure at this point which options will give the lowest power options ….?

Also, speed is still an issue as it will be important for future designs where we plan to use\port this design there.

Do you have any further suggestions ?

You'll probably need latch the data from the USB parrallel bits and request Avalon master bus cycles based on the latched values.

In some senses a UART interface might make this easier - split each uart data byte into two 4-bit fields, use one as 'command', the other as 'data'.

So a memory write would require upto 8 bytes to set the address, 8 bytes for the data and a final 'write' command (which might increment the address, and might set the last data nibble).

Read would be much the same except that you'd send 8 data bytes to the host.

That would be moderately slow - but probably not impossibly slow!

The shared memory access isn't an issue. All the internal memory is dual-ported and the Avalon 'bus' does arbitration.

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As an option, can any of these solutions be implemented without a NIOS and interfaced to memory internal to the SOPC builder via VHDL code?

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Yes.

I've written UART-to-Avalon-MM and FTDI FIFO-to-Avalon-MM master components. They implement an ASCII parser, so you can simply type "r <addr>\n" to read an address and "w <addr> <data>\n" to write an address.

This interface is not exactly high-speed, but its good enough for debug. A higher-speed interface would just need to use a slightly more complex protocol, eg., binary packets, much like the JTAG-to-Avalon-MM interface.

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I am looking to cut power as much as we can. However I am not certain if such a design will in fact take so much less power?

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Why are you using an FPGA if you are concerned about power?

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I assume that if we use a USB controller like the FX2 with the 8051 built in, it will be able to transfer the USB data to my memory internal to the SOPC system with no other internal interfacing required thus reducing the power requirements ?

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No matter what, you will always have to implement some logic in the FPGA. Any external device has interface timing requirements that need to be met.

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However there may be additional glue logic needed since there will be another NIOS attached this this internal memory and thus some sort of arbitration will be required

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That is why you should implement the logic as an Avalon-MM master.

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Also, speed is still an issue as it will be important for future designs where we plan to use\port this design there.

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What is the speed requirement?

Cheers,

Dave

dwh,

Thanks for your reply. What type of throughput have you achieved (MBytes\S) with your UART-to-Avalon-MM and FTDI FIFO-to-Avalon-MM master components ?

I assume that the FX2 would be able to acheive a much higher through put using its GPIF - 16-bit interface. The data sheets claims 96 Megabytes/s ! We are hoping that we will be able to program the 8051 so that it can directly map to an internal memory within the SOPC system.

Do you have any suggestions or comments on this ?

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What type of throughput have you achieved (MBytes\S) with your UART-to-Avalon-MM and FTDI FIFO-to-Avalon-MM master components ?

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I haven't checked. It was designed for convenience, not performance, i.e., no software development needed at either end.

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I assume that the FX2 would be able to acheive a much higher through put using its GPIF - 16-bit interface. The data sheets claims 96 Megabytes/s ! We are hoping that we will be able to program the 8051 so that it can directly map to an internal memory within the SOPC system.

Do you have any suggestions or comments on this ?

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I haven't had a chance to test either of these devices ...

The FX2 devices are 'fast' if the 8051 just 'gets out of the way'. You may not care whether or not your SOPC/Qsys system is mapped into the 8051 memory map, what you probably want is easy access from your host PC. In that case, implement a variation on the JTAG-to-Avalon-MM bridge protocol:

http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_analysis.pdf

i.e., the host sends the protocol bytes via USB to the FPGA, the FPGA logic implements the transaction and sends the response back to the host.

Cheers,

Dave

Dave,

Are you able to send me a copy of your FTDI FIFO-to-Avalon-MM master components ? Do you have any documentation of how it works and its interface ?

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Are you able to send me a copy of your FTDI FIFO-to-Avalon-MM master components ? Do you have any documentation of how it works and its interface?

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I haven't had a chance to document it yet. Its written in VHDL. Are you comfortable working with VHDL?

I plan on putting together an AlteraWiki tutorial to use the FTDI and UART components, but haven't had the time.

Do you have a board with an FTDI FT245 wired into it?

Cheers,

Dave

We are about to get a FT232H module in which we are hoping to be able to connect up to one of our current gate arrays. This chip has FIFO 245 interface !

Yes I am comfortable working with VHDL. Are you able to send me your design ?