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Altera_Forum
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21 years ago

Unexpected activity on a tri-state address bus

Hi,

I am working with NIOS II and a custom board.

I have made a board configuration with tri-state bus for my future SRAM/Flash... Right now I am not using it and I configured NIOS II IDE to place my code in the internal RAM and boot from EPCS. I have also internal timer device and some pios. The code does not access intentionally SRAM/Flash - it works with the pio only.

Using Signal tap in Quartus clocked with my cpu system clock I am seeing unexpected activity on my tri-state address bus but I do not see any chipselect signals activated. Addresses are selected to be in a sequence like 0000000x13 cycles, 0000988x2 cycles, 000098Cx2 cycles, back to 0000000 for 13 cycles, 000098C for 2 cycles, 0000000 for 13 cycles and back to 988 for 2, 98C for 2, 0000000 for 13 etc...

Am I seeing just random noise on the bus nobody controls now (no pull up/down resistors) or is it some activity caused by nios on the external pins?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    Hi Pszemol,

    This activity is legal as per Avalon; just as long as the accesses are not qualified with chipselect! Address and data bus values can be driven by what a master is doing with some other slave. Obviously for a tri-state bus, this will not be true of the data lines as they should be held high-impedance unless explicitly driven by an Avalon master accessing something on the bus. For other signals such as address/read/write, however, the signals from other bus transfers will show up on those signals.

    Hope this helps.
  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    --- Quote Start ---

    originally posted by jesse@Jun 30 2004, 04:19 PM

    this activity is legal as per avalon; just as long as the accesses are not qualified with chipselect! address and data bus values can be driven by what a master is doing with some other slave.

    --- Quote End ---

    Do I have any signal going from Avalon bus to actually turn on/off tri-state buffers to not "hear" this activity on external address pins configured in my FPGA as outputs for connecting them to my external SRAM/FLASH chips placed on my PCB?

    Or do I have to build such a signal for my internal "LPM_BUSTRI" tri-state buffer myself OR-ing any number of given chipselects? http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/dry.gif
  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    The latter. Not sure you want your address bus to float, though, so you may want to use AND or OR gates to make the bus idle at 0 or FFFFFFFF.

  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    Did the answers solve your problem?

    If not, We&#39;ll see what we can do.