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originally posted by jesse@Jun 30 2004, 04:19 PM
this activity is legal as per avalon; just as long as the accesses are not qualified with chipselect! address and data bus values can be driven by what a master is doing with some other slave. --- Quote End ---
Do I have any signal going from Avalon bus to actually turn on/off tri-state buffers to not "hear" this activity on external address pins configured in my FPGA as outputs for connecting them to my external SRAM/FLASH chips placed on my PCB?
Or do I have to build such a signal for my internal "LPM_BUSTRI" tri-state buffer myself OR-ing any number of given chipselects?
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