OK I did a check with signal tap, but a little bit different that how you told me.
here is the test code I used:
void test (void)
{
alt_u32 offset;
alt_u32 nWords = SDRAM_SPAN>>2;
alt_u32 pattern1 = 0xAAAAAAAA;
alt_u32 pattern2 = 0x55555555;
alt_u32 errCounter = 0;
alt_u32 firstErrorAddress = 0;
alt_u32 lastErrorAddress = 0;
alt_u32 lastError = 0;
// Test 1
// write 0xAAAAAAAA patern to all SDRAM cells
for (offset = 0; offset < nWords != 0; offset++) {
IOWR(SDRAM_BASE, offset, pattern1);
}
// read back 0xAAAAAAAA patern to all SDRAM cells
for (offset = 0; offset < nWords; offset++) {
if (IORD(SDRAM_BASE, offset) == pattern2) {
errCounter++;
}
}
errCounter = 0;
// Test 2
// write 0x55555555 patern to all SDRAM cells
for (offset = 0; offset < nWords != 0; offset++) {
IOWR(SDRAM_BASE, offset, pattern2);
}
// read back 0x55555555 patern to all SDRAM cells
for (offset = 0; offset < nWords; offset++) {
if (IORD(SDRAM_BASE, offset) == pattern1) {
lastError = offset;
if (errCounter == 0) {
firstErrorAddress = offset;
}
else {
}
errCounter++;
}
else {
if ((offset - lastError) == 1) {
lastErrorAddress = offset - 1;
}
else {
}
}
}
}
At debug startup I check the SDRAM content (with the memory monitor) to see about what kind of values are present. And I can see about everything (that normal because no data has been written yet)
step 1:
I placed a breakpoint at end of first loop (writing 0xAAAAAAAA into entire SDRAM) and set signal tap trigger to SDRAM data bus with 0x55555555 pattern trigger. I ran to code until break point and nothing triggered in signal tap (it's normal but I can be sure that the 0x55555555 pattern as never been sent to SDRAM)
step 2:
I placed a breakpoint at end of second loop (reading 0xAAAAAAAA from entire SDRAM) and still set signal tap trigger to SDRAM data bus with 0x55555555 pattern trigger. I ran to code until break point and nothing triggered in signal tap(still normal but I can be sure that no 0x55555555 pattern is present inside SDRAM)
step 3:
I placed a breakpoint at end of third loop (writing 0x55555555 into entire SDRAM) and set signal tap trigger to SDRAM data bus with 0xAAAAAAAA pattern trigger. I ran to code until break point and nothing triggered in signal tap (it's normal but I can be sure that the 0xAAAAAAAA pattern as never been sent to SDRAM)
step 4:
I placed a breakpoint at end of fourth loop (reading 0x55555555 from entire SDRAM) and still set signal tap trigger to SDRAM data bus with 0xAAAAAAAA pattern trigger. I ran to code until break point and here a lot of trigger occured in signal tap (1256917 times)! So a lot of cells content (or address lines) seem corrupted or defect! It is about 30% of entire SDRAM, between offset 0x0000000E and 0x003FFFF4 (in 32bit step address mode) So it is about the entire range, not specially around a region.
I think it is an hardware issue but it is little bit strange because I worked a lot of hours with this hardware and with the main firmware running in SDRAM without any error, crash or strange functionality!
Have you got an idea if I can do another test?
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