uncontrolled SDRAM content change

I recommend capturing the data in signaltap at the slave port of the SDRAM. Put a trigger on the base address of the test being written as well as a break condition between two loops in your last post. When you run the code you should see whatever value 'pattern1' is written to the slave port. Now that the CPU is stopped on the break point, prepare signaltap to trigger on the base address of the test being read, once that's ready hit the advance button in the debugger which should let that second loop run to completion. Verify whatever data 'pattern1' is that it was read out correctly since this can help you figure out of you are looking at a hard or software issue.

Note: To trigger both of those I would setup the trigger for the address to be whatever the base address of your test is (remember this is a word offset if you signaltap it at the SDRAM slave port) and ((rising edge write) or (rising edge read)). Capturing on either rising edge should ensure the same trigger will work for both loops (writes and reads).

Simulations couldn't hurt either, it's just that if you have a hardware issue like pins not constrained properly or mis-wired simulations will not find those.