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Patrik78's avatar
Patrik78
Icon for New Contributor rankNew Contributor
3 years ago

UART IP - waitrequest signal

Hello to everybody,

working with Platform Designer (Quartus 21.1) I'm facing something strange: I'm trying to interface the UART CORE IP with a custom hardware. But I noticed the IP is missing any flowcontrol signals.

So how to understand if the UART has received something, possibly avoid polling technique ?

As far as I know the old dataready signal is now deprecated, and is suggested to use waitrequest signal. But it seems even this signal is not implemented in the standard UART IP.

Trying to connect my custom hardware with UART IP I get this message "Interconnect is inserted between master and slave, because master has waitrequest signal 1 bit wide, but slave is 0 bit wide"

Moreover what if I want to connect directly to a DMA ?

Thanks for your help.

14 Replies

  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi Patrik78,


    I will get back to you regarding the info to your question.


    Thanks.

    Regards,

    Aik Eu


  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    FYI, the enablement of the CTS/RTS in the IP settings.

    Thanks.

    Regards,

    Aik Eu

  • Patrik78's avatar
    Patrik78
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hi Aik,

    actually RTS and CTS are signals on UART side, my goal is to get flow control signals on Avalon side.

    In other words a standard avalon interface is not able to know if the IP has received data from uart side, except for polling technique.

  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi Patrik78,


    I am consulting engineering at the moment for that particular IP. It will take some time for respond. Sorry for the inconvenience.


    Thanks.

    Regards,

    Aik Eu


  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi Patrik78,


    The control register bit of the UART IP, IRRDY will required to be enabled if using interrupt instead of a polling technique.

    "irrdy - Enable interrupt for a receive character ready"

    the irq is sent to the HPS side, which has an interrupt receiver port

    There is no port to detect the interrupt in the avalon interface side.


    Besides that, user can consider using a new Lightweight UART IP (releasing in 22.3) which having TXFIFO and RXFIFO. With this, a DMA is not required


    Thanks.

    Regards,

    Aik Eu


  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi Patrik78,


    Do you have any further question regarding the previous comment?


    Thanks.

    Regards,

    Aik Eu


  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi Patrik78,


    I will close this thread if no further question.


    Thanks.

    Regards,

    Aik Eu


  • Patrik78's avatar
    Patrik78
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hello,

    if I understand correctly, there's no way to use the UART IP with DMA except the use of a device with HPS.

    This is really a bad thing to hear, but ok I have no other question.

  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi Patrik78,


    Sorry that I mentioned incorrectly about HPS as your system which is using Nios ii.

    The irq should be sent to the Nios ii interrupt reciver port.

    The control register bit of the UART IP, IRRDY will required to be enabled if using interrupt instead of a polling technique.

    "irrdy - Enable interrupt for a receive character ready"


    Thanks.

    Regards,

    Aik Eu