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Patrik78's avatar
Patrik78
Icon for New Contributor rankNew Contributor
4 years ago

UART IP - waitrequest signal

Hello to everybody, working with Platform Designer (Quartus 21.1) I'm facing something strange: I'm trying to interface the UART CORE IP with a custom hardware. But I noticed the IP is missing any ...
aikeu's avatar
aikeu
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Patrik78,


The control register bit of the UART IP, IRRDY will required to be enabled if using interrupt instead of a polling technique.

"irrdy - Enable interrupt for a receive character ready"

the irq is sent to the HPS side, which has an interrupt receiver port

There is no port to detect the interrupt in the avalon interface side.


Besides that, user can consider using a new Lightweight UART IP (releasing in 22.3) which having TXFIFO and RXFIFO. With this, a DMA is not required


Thanks.

Regards,

Aik Eu