UART IP - waitrequest signal
Hello to everybody,
working with Platform Designer (Quartus 21.1) I'm facing something strange: I'm trying to interface the UART CORE IP with a custom hardware. But I noticed the IP is missing any flowcontrol signals.
So how to understand if the UART has received something, possibly avoid polling technique ?
As far as I know the old dataready signal is now deprecated, and is suggested to use waitrequest signal. But it seems even this signal is not implemented in the standard UART IP.
Trying to connect my custom hardware with UART IP I get this message "Interconnect is inserted between master and slave, because master has waitrequest signal 1 bit wide, but slave is 0 bit wide"
Moreover what if I want to connect directly to a DMA ?
Thanks for your help.