u-boot on the nios2 eval baord

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originally posted by smcnutt@Apr 14 2006, 12:09 PM

> are you sure it's 80mhz. i seem to recal seeing 66mhz in sopc builder.

ok ... i've been looking at the 'standard' configuration ... which is 80 mhz. if you're

using the 'full featured' configuration, then 66 mhz is correct.

regards,

--scott

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Thanks Scott for the reply, but I have one more question:

Why would full feature use a 66MHZ clok and standard uses a 80MHZ clock?

Does the number of functional blocks determine the clock speed and if so, why?

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originally posted by smcnutt@Apr 14 2006, 12:09 PM

> are you sure it&#39;s 80mhz. i seem to recal seeing 66mhz in sopc builder.

ok ... i&#39;ve been looking at the &#39;standard&#39; configuration ... which is 80 mhz. if you&#39;re

using the &#39;full featured&#39; configuration, then 66 mhz is correct.

regards,

--scott

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=14391)

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Ok Scott,

I have lift off, but only on the JTAG UART. Thanks for your help. Next task, get the _real_ UART working...

> Why would full feature use a 66MHZ clok and standard uses a 80MHZ clock?

> Does the number of functional blocks determine the clock speed and if so, why?

As more "area" is consumed by your design, it becomes increasingly difficult to

route signals through the available interconnect paths. When things get crowded,

critical paths get longer and propagation delays increase -- so you have to slow

down the clock to meet the required setup, hold, etc. times.

> I have lift off, but only on the JTAG UART.

Great!

Regards,

--Scott