Honored ContributorDear All,
Does anyone know what could cause the MAC software reset procedure doesn't complete? I mean bit SW_RESET never get cleared. Thank a lot in advance.
Honored ContributorI actually use macros from triple_speed_ethernet.h to acces the MAC and PHY. I'm pretty sure they are all derived from IOWR/IORD. I would assume that an unconfigured PHY could cause the MAC sw_reset never ends.
Thanks DAIXIWEN and Cris72.Honored ContributorWhat PHY chip are you using? You can put some signaltap probes on the signals between the PHY and the MAC to check if the clocks are there, and if you can spot an difference between the working and the failing design.
Honored ContributorI'm using Marvell 88e1111. I will do the check this morning.
Honored ContributorHi guys,
I checked if rxclock at RGMII interface trough Signal Tap LA. rx_clk it's always there, even after a power up and PHY is not yet initialized.Honored ContributorThere seems to be a special procedure to set the driver/TSE/PHY in RGMII mode. I'm not sure this would affect the reset procedure though... Did you do it?
http://www.altera.com/support/kdb/solutions/rd11122009_293.htmlHonored ContributorNo, I didn't. I'm directly accessing TSE MAC register not using any driver.
Honored ContributorFrom Altera's driver there are two interesting functions for your case
/* @Function Description: Perform switching of the TSE MAC into GMII (Gigabit) mode.
* COMMAND_CONFIG register is restored after reset.
* @API Type: Public
* @param pmac Pointer to the TSE MAC Control Interface Base address
*/
alt_32 tse_mac_setGMIImode(np_tse_mac *pmac)
{
alt_32 helpvar;
helpvar = IORD_ALTERA_TSEMAC_CMD_CONFIG(pmac);
helpvar |= ALTERA_TSEMAC_CMD_ETH_SPEED_MSK;
IOWR_ALTERA_TSEMAC_CMD_CONFIG(pmac,helpvar);
return SUCCESS;
}/* @Function Description: Change operating mode of Marvell PHY to RGMII
* @API Type: Internal
* @param pmac Pointer to the first TSE MAC Control Interface Base address within MAC group
*/
alt_32 marvell_cfg_rgmii(np_tse_mac *pmac) {
alt_u16 dat = IORD(&pmac->mdio1.reg1b, 0);
dat &= 0xfff0;
tse_dprintf(5, "MARVELL : Mode changed to RGMII/Modified MII to Copper mode\n");
IOWR(&pmac->mdio1.reg1b, 0, dat | 0xb);
tse_dprintf(5, "MARVELL : Enable RGMII Timing Control\n");
dat = IORD(&pmac->mdio1.reg14, 0);
dat &= ~0x82;
dat |= 0x82;
IOWR(&pmac->mdio1.reg14, 0, dat);
tse_dprintf(5, "MARVELL : PHY reset\n");
dat = IORD(&pmac->mdio1.CONTROL, 0);
IOWR(&pmac->mdio1.CONTROL, 0, dat | PCS_CTL_sw_reset);
return 1;
}that's very interesting DAIXIWEN,
I do almost the same things in my code but, in this code:alt_32 marvell_cfg_rgmii(np_tse_mac *pmac) {
alt_u16 dat = IORD(&pmac->mdio1.reg1b, 0);
dat &= 0xfff0;
tse_dprintf(5, "MARVELL : Mode changed to RGMII/Modified MII to Copper mode\n");
IOWR(&pmac->mdio1.reg1b, 0, dat | 0xb);
tse_dprintf(5, "MARVELL : Enable RGMII Timing Control\n");
dat = IORD(&pmac->mdio1.reg14, 0);
dat &= ~0x82;
dat |= 0x82;
IOWR(&pmac->mdio1.reg14, 0, dat);
tse_dprintf(5, "MARVELL : PHY reset\n");
dat = IORD(&pmac->mdio1.CONTROL, 0); IOWR(&pmac->mdio1.CONTROL, 0, dat | PCS_CTL_sw_reset);
return 1; This if_Mode register (word address 0x94) is there only if you enable the PCS. If not this address it will map to the register 0x14 of the PHY whose address is configured in mdio_addr0.
The mdio1.reg14 (word address 0xb4) will always map to the register 0x14 of the PHY whose address is configured in mdio_addr1. The TSE driver is probably using the mdio1 address space instead of mdio0 so that it can support the configurations with PCS enabled (as in this case the PCS registers are placed in the mdio0 space).Honored Contributorok, now I undersand. So definitely I do the same things in my code.
