TSE MAC Software Reset doesn't complete

Are the rx and tx clock signals correctly driven?

Is the hw reset pin deasserted?

Yes, hw_reset is deasserted. Which side rx, tx clock signal do you mean? PHY side or avalon streaming side?

In the meanwhile i found a code implementation that doesn't have this problem. Do you think that PHY configuration, and then state, can have an impact on the MAC sw_reset completion?

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In the meanwhile i found a code implementation that doesn't have this problem. Do you think that PHY configuration, and then state, can have an impact on the MAC sw_reset completion?

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Do you mean you are running a different Nios code with the same fpga configuration?

Or have you rebuild the fpga with Quartus, too?

Are you using the standard Altera drivers? What operating system? The standard drivers avoid the cache when reading that bit.

Usually this problem is due to lack of clocks from the PHY side, so you should check that first.

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Do you mean you are running a different Nios code with the same fpga configuration?

Or have you rebuild the fpga with Quartus, too?

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I mean same FPGA configuration but sligthly different NIOS application code.

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Are you using the standard Altera drivers? What operating system? The standard drivers avoid the cache when reading that bit.

Usually this problem is due to lack of clocks from the PHY side, so you should check that first.

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I'm not using any driver and any OS. I have a single thread application.

I have two functions, PhyInit() and MACInit(). At a first glance I would have put them this order:

MACInit();

PhyInit();

but in this way MAC sw_reset doesn't complete but it does if I put them in the opposite order.

Do you mean that a lack of rxclock at the PHY-MAC interface could induce that problem?

what does "avoid the cache" mean?

One of the tasks performed by sw_reset function is flushing the rx fifo.

I don't know TSE MAC inner workings, but I guess that an uninitialized phy or a missing rx clock could prevent this operation from completing.

yes this problem could come from the lack of a rxclock on the interface between the MAC and the PHY.

By "avoid the cache" I mean access the MAC registers through the IORD/IOWR macros, or uned an uncached pointer. If you just use a regular C pointer/structure to read the mac's registers then there is a good chance that you read a value stored in the CPU's data cache rather than the real register.