TLB Miss Exception

As you can see from the .ptf (which is the real thing about sopc builder), the addresses were chosen to be at physical address in the lowest memory.

        
         reset_slave = "altmemddr_0/s1";
         break_slave = "cpu_0/jtag_debug_module";
         exc_slave = "altmemddr_0/s1";
         reset_offset = "0x00000020";
         break_offset = "0x00000020";
         exc_offset = "0x00000060";

You can find the ptf file in attachment

You can also find and image of the CPU configuration screen.

This is a custom design on a custom board. I have chosen to put the reset and exception vectors in these positions as a suggestion from the Altmemphy manual: on page 21 of emi_ddr_ug.pdf, I have found that the calibration process uses addresses between 0x0 and 0x1F. This can be avoided once I load my system from flash, because it is i a safe place at reset.

The DDR2 Controller I am using is based on Altmemphy and not Uniphy. So this is why I have chosen these addresses. Anyway I made a mistake, the addresses MUST be calculated multiplying the range for the bus dimension in bytes. On the other hand the kernel is not loading after a reset (it is downloaded via JTAG) so this should not be corrupted.

Anyway, the only constraint I remember about position is that they must be in the 0x0-0x1FFFFFFF memory range; obviously there must be enough space for the code and variables.

Then the sopc-create-header-files --single imcpu_fpga.h script generates the map translating all addresses in virtual memory. I am not sure that the point is in this translation, I have tracked a lot of system calls and other stuff (exceptions, interrupts or traps are considered exceptions as I know).

I have found that the instruction corresponding to the ea register is the stb instruction called from the macro put_user_asm, which is called from the macro __put_user_common, which is called from the macro __put_user which is called by the function __clear_user (arch/nios2/mm/uaccess.c).

I'll try to recompile with a different reset and break address. As you suggested.

Hello!

You are right. Thanks a lot!

With the exception vector placed at 0x20 it arrives at the shell. It also allows me to give some commands. Great!!

It is not my intention to make an offense or tell waht is good and what is not but I can not find an explanation for this. I mean:I did not find anywhere this information in Nios II Datasheets or in the wiki. I found suggestions and examples but not constraints.

I may have jumped a few lines in the pdf or website and lost this thing.

However, I'll try to track where this difference in addresses makes a difference in software behaviour. I'll keep the community informed if I find something. Please let me know if I missed something in the documentation. Thanks,

Regards,

Gabriele Gobbin

Hello!

just for information to anyone, hoping this avoids problems to other users.

There is a constraint for the Reset Vecotr Address which seems to be untold. The constraints does not depends on Nios II architecture so it is not found on Altera documentation. It depends on the Kernel image generation process and, in my personal opinion, should be told in the wiki documentation.

The kernel image construction does not depend on the FPGA memory map but depends on Nios II MMU Memory partitioning.

The assembler code in arch/nios2/kernel/head.S copies the exc_hook to the address specified in SOPC Builder. Then it copies the fast tlb miss handler to the specified address. The problem in my configuration is that the exception address configured in SOPC Builder is where at the moment the fast tlb miss handler code resides so the exception handler is copied inside the tlb miss handler.

At the moment a FIXUP comment exists in the file. A possible fixup is to write some instructions that verify which label is to be copied first but it could be a patch valid only for a small set of problems. I suggest that the wiki should be updated, to whom do I need to talk?

Thanks,

Gabriele Gobbin