As you can see from the .ptf (which is the real thing about sopc builder), the addresses were chosen to be at physical address in the lowest memory.
reset_slave = "altmemddr_0/s1";
break_slave = "cpu_0/jtag_debug_module";
exc_slave = "altmemddr_0/s1";
reset_offset = "0x00000020";
break_offset = "0x00000020";
exc_offset = "0x00000060";
You can find the ptf file in attachment
You can also find and image of the CPU configuration screen.
This is a custom design on a custom board. I have chosen to put the reset and exception vectors in these positions as a suggestion from the Altmemphy manual: on page 21 of emi_ddr_ug.pdf, I have found that the calibration process uses addresses between 0x0 and 0x1F. This can be avoided once I load my system from flash, because it is i a safe place at reset.
The DDR2 Controller I am using is based on Altmemphy and not Uniphy. So this is why I have chosen these addresses. Anyway I made a mistake, the addresses MUST be calculated multiplying the range for the bus dimension in bytes. On the other hand the kernel is not loading after a reset (it is downloaded via JTAG) so this should not be corrupted.
Anyway, the only constraint I remember about position is that they must be in the 0x0-0x1FFFFFFF memory range; obviously there must be enough space for the code and variables.
Then the sopc-create-header-files --single imcpu_fpga.h script generates the map translating all addresses in virtual memory. I am not sure that the point is in this translation, I have tracked a lot of system calls and other stuff (exceptions, interrupts or traps are considered exceptions as I know).
I have found that the instruction corresponding to the ea register is the stb instruction called from the macro put_user_asm, which is called from the macro __put_user_common, which is called from the macro __put_user which is called by the function __clear_user (arch/nios2/mm/uaccess.c).
I'll try to recompile with a different reset and break address. As you suggested.