TLB Miss Exception

Hello!

just for information to anyone, hoping this avoids problems to other users.

There is a constraint for the Reset Vecotr Address which seems to be untold. The constraints does not depends on Nios II architecture so it is not found on Altera documentation. It depends on the Kernel image generation process and, in my personal opinion, should be told in the wiki documentation.

The kernel image construction does not depend on the FPGA memory map but depends on Nios II MMU Memory partitioning.

The assembler code in arch/nios2/kernel/head.S copies the exc_hook to the address specified in SOPC Builder. Then it copies the fast tlb miss handler to the specified address. The problem in my configuration is that the exception address configured in SOPC Builder is where at the moment the fast tlb miss handler code resides so the exception handler is copied inside the tlb miss handler.

At the moment a FIXUP comment exists in the file. A possible fixup is to write some instructions that verify which label is to be copied first but it could be a patch valid only for a small set of problems. I suggest that the wiki should be updated, to whom do I need to talk?

Thanks,

Gabriele Gobbin